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| APA2037 3W Stereo Fully Differential Audio Power Amplifier Features General Description The APA2037 is a stereo, fully differential Class-AB audio amplifier which can operate with supply voltage from 2.4V to 5V and is available in a TQFN5x5-20A package. The built-in feedback resistors can minimize the external component counts and save the PCB space. High PSRR and fully differential architecture increase immunity to noise and RF rectification. In addition to these features, a short startup time and small package size make the APA2037 is an ideal choice for LCD TVs and notebook PCs and Portable devices. The APA2037 also integrates the de-pop circuitry that reduces the pops and click noises during power on/off and shutdown mode operation. Both Thermal and over-current protections are integrated to avoid the IC to be destroyed by over temperature and short-circuit. The APA2037 is capable of driving 3W at 5V into 3 speaker. * * * * * * * * * Operating Voltage: 2.4V~5.5V Fully Differential Class-AB Amplifier High PSRR and Excellent RF Rectification Immunity Low Crosstalk 3W Per Channel Output Power into 3 Load at VDD=5V Thermal and Over-Current Protections Built-in Feedback Resistors Eliminate External Components Counts Space Saving Package - TQFN5x5-20A Lead Free and Green Devices Available (RoHS Compliant) Applications 15 RBYPASS Simplified Application Circuit RINP 16 11 LBYPASS * * * LCD TVs Notebook, PCs Portable Devices Pin Configuration 13 LINN 12 LINP 14 RSD 10 NC 9 LSD Left Channel Input LINN LINP LOUTP LOUTN Left Channel Speaker RINN 17 NC 18 RVDD 19 NC 20 TQFN5x5-20A Top View 8 NC 7 LVDD 6 LOUTN APA2037 ROUTN Right Channel Input RINP RINN ROUTP Right Channel Speaker ROUTP 1 GND 2 ROUTN 3 LOUTP 4 =Thermal Pad (connected the Thermal Pad to GND plane for better heat dissipation) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 1 www.anpec.com.tw GND 5 APA2037 Ordering and Marking Information APA2037 Assembly Material Handling Code Temperature Range Package Code APA2037 QB : APA2037 XXXXX Package Code QB : TQFN5x5-20A Operating Ambient Temperature Range I : -40 to 85 C Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device XXXXX - Date Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD020C for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol VDD VIN TJ TSTG TSDR PD (Note 1) (Over operating free-air temperature range unless otherwise noted.) Parameter Supply Voltage (LVDD, RVDD to GND) Input Voltage (LINN, LINP, RINN, RINP, LSD, RSD to GND) Maximum Junction Temperature Storage Temperature Range Maximum Lead Soldering Temperature, 10 Seconds Power Dissipation Rating -0.3 to 6 -0.3 to VDD+0.3 150 -65 to +150 260 Internally Limited Unit V V C C C W Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol Parameter Thermal Resistance -Junction to Ambient Thermal Resistance -Junction to Case TQFN5x5-20A (Note 2) TQFN5x5-20A (Note 3) Typical Value 40 8 Unit JA JC C/W C/W Note 2: Please refer to " Layout Recommendation", the Thermal Pad on the bottom of the IC should soldered directly to the PCB' s ThermalPad area that with several thermal vias connect to the ground plan, and the PCB is a 2-layer, 5-inch square area with 2oz copper thickness. Note 3: The case temperature is measured at the center of the Thermal Pad on the underside of the TQFN5X5-32A package. Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 2 www.anpec.com.tw APA2037 Recommended Operating Conditions Symbol VDD VIH VIL VIC Supply Voltage High Level Threshold Voltage Low Level Threshold Voltage Common Mode Input Voltage Operating Ambient Temperature Range Operating Junction Temperature Range Speaker Resistance LSD, RSD LSD, RSD Parameter Range 2.4 ~ 5.5 1.8 ~VDD 0 ~ 0.35 0.5 ~ VDD-0.5 -40 ~ 85 -40 ~ 125 3~ Unit V V V C C Electrical Characteristics VDD=5V, Gnd=0V, TA= 25 C (unless otherwise noted) Symbol IDD ISD II Gain TSTART-UP RSD Start-Up Time from End of Shutdown Resistance from Shutdown to GND Parameter Supply Current Shutdown Current Input Current LSD = RSD = 0V LSD, RSD RL=4 Cb1=Cb2 = 0.22F Test Conditions Min. 36k Ri 90 APA2037 Typ. Max. 6 12 1 0.1 40k Ri 65 100 5 44k Ri 110 Unit mA A A V/V ms k o VDD=5V, TA=25X C RL = 3 THD+N = 1% PO Output Power THD+N = 10% fin = 1kHz RL = 4 RL = 8 RL = 3 RL = 4 RL = 8 THD+N Crosstalk PSRR CMRR S/N VOS Vn Total Harmonic Distortion Pulse Noise Channel separation Power Supply Rejection Ratio Common-Mode Rejection Ratio Signal to Noise Ratio Output Offset Voltage Noise Output Voltage fin = 1kHz RL = 4 PO= 1.5W RL = 8 PO= 0.9W 1 2.4 2.1 1.3 3 2.6 1.6 0.05 0.035 105 80 60 105 5 15 % 20 dB mV V (rms) dB W PO=130mW, RL =8, fin = 1kHz Cb1 = Cb2= 0.22F, RL = 8, VRR=0.2VPP, fin = 217Hz Cb1 = Cb2= 0.22F, RL = 8, VIC=0.2VPP, fin = 217Hz With A-weighting Filter PO = 1.3W, RL = 8 RL = 8 Cb1 = Cb2= 0.22F, With A-weighting Filter Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 3 www.anpec.com.tw APA2037 Electrical Characteristics (Cont.) VDD=5V, GND=0V, TA= 25 C (unless otherwise noted) Symbol VDD=3.6V, TA=25X C RL = 3 THD+N = 1% PO Output Power THD+N = 10% fin = 1kHz RL = 4 RL = 8 RL = 3 RL = 4 RL = 8 THD+N Crosstalk PSRR CMRR S/N VOS Vn Total Harmonic Distortion Pulse Noise Channel separation Power Supply Rejection Ratio Common-Mode Rejection Ratio Signal to Noise Ratio Output Offset Voltage Noise Output Voltage fin = 1kHz RL = 4 PO = 0.7W RL = 8 PO= 0.45W 1.2 1 0.65 1.5 1.3 0.8 0.07 0.05 105 78 60 103 5 15 % dB 20 mV V (rms) W Parameter Test Conditions Min. APA2037 Typ. Max. Unit o PO=65mW, RL=8, fin=1kHz Cb1 = Cb2= 0.22F, RL = 8, VRR=0.2VPP, fin = 217Hz Cb1 = Cb2= 0.22F, RL = 8, VIC=0.2VPP, fin = 217Hz With A-weighting Filter PO = 0.65W, RL = 8 RL = 8 Cb1 = Cb2= 0.22F, With A-weighting Filter RL = 3 THD+N = 1% RL = 4 RL = 8 RL = 3 THD+N = 10% fin = 1kHz RL = 4 RL = 8 PO = 0.3W, RL = 4 fin = 1kHz PO = 0.2W, RL = 8 PO=30mW, RL=8, fin=1kHz Cb1 = Cb2= 0.22F, RL = 8, VRR=0.2VPP, fin = 217Hz Cb1 = Cb2= 0.22F, RL = 8, VIC=0.2VPP, fin = 217Hz With A-weighting Filter PO = 0.3W, RL = 8 RL = 8 Cb1 = Cb2= 0.22F, With A-weighting Filter VDD=2.4V, TA=25X C 0. 5 0.45 0.3 0.7 0.6 0.35 0.1 0.08 105 75 60 100 5 15 % 20 mV V (rms) dB W PO Output Power THD+N Crosstalk PSRR CMRR S/N VOS Vn Total Harmonic Distortion Pulse Noise Channel Separation Power Supply Rejection Ratio Common-Mode Rejection Ratio Signal to Noise Ratio Output Offset Voltage Noise Output Voltage Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 4 www.anpec.com.tw APA2037 Pin Description PIN NO. 1 2,5 3 4 6 7 8,10,18,20 9 11 12 13 14 15 16 17 19 NAME ROUTP GND ROUTN LOUTP LOUTN LVDD NC LSD LBYPASS LINP LINN RSD RBYPASS RINP RINN RVDD I/O/P O P O O O P I P I I I P I I P FUNCTION The right channel positive output terminal of speaker amplifier. Ground connection for circuitry. The right channel negative output terminal of speaker amplifier The left channel positive output terminal of speaker amplifier. The left channel negative output terminal of speaker amplifier. Left channel supply voltage input pin. No connection. Left channel shutdown mode control signal input pin, place left channel speaker amplifier in shutdown mode when held low. Left channel bypass voltage input pin. The non-inverting input of left channel amplifier. LINP is connected to ground (Gnd node) via a capacitor for single-end (SE) input signal. The inverting input of left channel amplifier. LINN is used as audio input terminal, typically. Right channel shutdown mode control signal input pin, place left channel speaker amplifier in shutdown mode when held low. Right channel bypass voltage input pin. The non-inverting input of right channel amplifier. RINP is connected to ground (Gnd node) via a capacitor for single-end (SE) input signal. The inverting input of right channel amplifier. RINN is used as audio input terminal, typically. Right channel supply voltage input pin Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 5 www.anpec.com.tw APA2037 Typical Operating Characteristics THD+N vs. Output Power 10 RL=3 fin=1kHz Ci=0.22F AV=12dB BW<80kHz THD+N vs. Output Power 10 RL=4 fin=1kHz Ci=0.22F AV=12dB BW<80kHz 1 THD+N (%) 1 VDD=2.4V THD+N (%) VDD=2.4V 0.1 VDD=3.6V VDD=5.0V 0.1 VDD=3.6V VDD=5.0V 0.01 10m 100m 1 5 Output Power (W) 0.01 10m 100m 1 5 Output Power (W) THD+N vs. Output Power 10 THD+N vs. Frequency 10 VDD=5.0V RL=3 Ci=0.22F AV=12dB BW<80kHz RL=8 fin=1kHz Ci=0.22F AV=12dB BW<80kHz THD+N (%) VDD=2.4V 0.1 VDD=3.6V VDD=5.0V THD+N (%) 1 1 0.1 PO=1W PO=1.7W 0.01 10m 100m 1 3 0.01 20 100 1k 10k 20k Output Power (W) Frequency (Hz) THD+N vs. Frequency 10 VDD=5.0V RL=4 Ci=0.22F AV=12dB BW<80kHz THD+N vs. Frequency 10 VDD=5.0V RL=8 Ci=0.22F AV=12dB BW<80kHz THD+N (%) 1 0.1 PO=1W THD+N (%) 1 0.1 PO=0.5W PO=1.5W PO=0.9W 0.01 20 100 1k 10k 20k 0.01 20 100 1k 10k 20k Frequency (Hz) Frequency (Hz) Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 6 www.anpec.com.tw APA2037 Typical Operating Characteristics (Cont.) THD+N vs. Frequency 10 VDD=3.6V RL=4 Ci=0.22F AV=12dB BW<80kHz 10 VDD=3.6V RL=8 Ci=0.22F AV=12dB BW<80kHz PO=0.1W THD+N vs. Frequency THD+N (%) PO=0.1W PO=0.5W PO=0.7W THD+N (%) 1 1 0.1 PO=0.25W 0.1 PO=0.45W 0.01 20 100 1k 10k 20k 0.01 20 100 1k 10k 20k Frequency (Hz) Frequency (Hz) THD+N vs. Frequency 10 VDD=2.4V RL=4 Ci=0.22F AV=12dB BW<80kHz THD+N vs. Frequency 10 VDD=2.4V RL=8 Ci=0.22F AV=12dB BW<80kHz THD+N (%) 1 0.1 PO=0.1W PO=0.3W THD+N (%) 1 0.1 PO=0.1W PO=0.2W 0.01 20 100 1k 10k 20k 0.01 Frequency (Hz) 20 100 1k 10k 20k Frequency (Hz) Output Power vs. Supply Voltage 3.5 3.0 fin=1kHz RL=3,THD+N=10% AV=12dB Mono RL=4,THD+N=10% RL=3,THD+N=1% RL=4,THD+N=1% 1.5 1.0 0.5 0.0 RL=8,THD+N=10% RL=8,THD+N=1% 2.4 3.0 3.5 4.0 4.5 5.0 3.5 Output Power vs. Load Resistance VDD=5V,THD+N=10% 3.0 VDD=5V,THD+N=1% fin=1kHz AV=12dB Mono Output Power (W) Output Power (W) 2.5 2.0 2.5 2.0 1.5 VDD=3.6V,THD+N=10% VDD=3.6V,THD+N=1% VDD=2.4V,THD+N=10% VDD=2.4V,THD+N=1% 1.0 0.5 0.0 3 8 13 18 23 28 32 Supply Volume (V) Load Resistance () Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 7 www.anpec.com.tw APA2037 Typical Operating Characteristics (Cont.) Power Dissipation vs. Output Power 2.0 1.0 Power Dissipation vs. Output Power Power Dissipation (W) 1.5 RL=3 1.0 RL=4 Power Dissipation (W) 0.8 RL=3 0.6 RL=4 0.4 VDD=3.6V fin=1kHz AV=12dB Mono 1.2 1.5 1.8 0.5 RL=8 VDD=5V fin=1kHz AV=12dB Mono 2.0 2.5 3.0 0.2 RL=8 0.0 0.0 0.3 0.6 0.9 0.0 0.0 0.5 1.0 1.5 Output Power (W) Output Power (W) Supply Current vs. Output Power 1.0 RL=3 0.8 0.8 Supply Current vs. Output Power RL=3 0.6 Supply Current (A) 0.6 RL=4 0.4 RL=8 0.2 VDD=5V fin=1kHz AV=12dB Mono 0.5 1.0 1.5 2.0 2.5 3.0 Supply Current (A) 0.4 RL=4 0.2 RL=8 VDD=3.6V fin=1kHz Av=12dB Mono 0.3 0.6 0.9 1.2 1.5 1.8 0.0 0.0 0.0 0.0 Output Power (W) Output Power (W) Crosstalk vs. Frequency +0 -20 -40 T =5.0V VDDTTT RL=3 AV=12dB Ci=0.22F PO=240mW Crosstalk vs. Frequency +0 -20 -40 TT VDD=5.0V RL=4 AV=12dB Ci=0.22F PO=210mW Crosstalk (dB) Crosstalk (dB) -60 -80 Right to Left -60 -80 Right to Left -100 -120 -140 20 Left to Right -100 -120 -140 100 1k 10k 20k Left to Right 20 100 1k 10k 20k Frequency (Hz) Frequency (Hz) Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 8 www.anpec.com.tw APA2037 Typical Operating Characteristics (Cont.) Crosstalk vs. Frequency +0 -20 -40 T VDD=5.0V RL=8 AV=12dB Ci=0.22F PO=130mW Crosstalk (dB) -60 -80 -100 -120 -140 20 Right to Left Crosstalk (dB) TTT TT VDD=3.6V -20 RL=4 AV=12dB Ci=0.22F -40 P =100mW O -60 -80 Right to Left Left to Right +0 Crosstalk vs. Frequency -100 -120 -140 20 Left to Right 100 1k 10k 20k 100 1k 10k 20k Frequency (Hz) Frequency (Hz) Crosstalk vs. Frequency +0 TTTTT VDD=3.6V RL=8 -20 AV=12dB Ci=0.22F -40 PO=65mW -60 -80 Right to Left -100 -120 -140 Left to Right Crosstalk vs. Frequency +0 TTTTT T T VDD=2.4V RL=4 -20 AV=12dB Ci=0.22F -40 PO=45mW -60 -80 Right to Left Left to Right -120 -140 Crosstalk (dB) Crosstalk (dB) -100 20 100 1k 10k 20k 20 100 1k 10k 20k Frequency (Hz) Frequency (Hz) Crosstalk vs. Frequency TTTTT TT VDD=2.4V -20 RL=8 AV=12dB Ci=0.22F -40 PO=30mW -60 -80 Right to Left +0 Output Noise Voltage vs. Frequency 50u Output Noise Voltage (Vrms) 20u Left channel Right channel Crosstalk (dB) 10u -100 Left to Right -120 -140 20 100 1k 10k 20k Frequency (Hz) 1u 20 VDD=5.0V RL=8 AV=12dB Ci=0.22F A-Weighting 100 1k 10k 20k Frequency (Hz) Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 9 www.anpec.com.tw APA2037 Typical Operating Characteristics (Cont.) Output Noise Voltage vs. Frequency 50u Output Noise Voltage vs. Frequency 50u Output Noise Voltage (Vrms) 20u Right channel Left channel Output Noise Voltage (Vrms) 20u Right channel Left channel 10u 10u VDD=3.6V RL=8 AV=12dB Ci=0.22F A-Weighting 1u 20 100 1k 10k 20k VDD=2.4V RL=8 AV=12dB Ci=0.22F A-Weighting 1u 20 100 1k 10k 20k Frequency (Hz) Frequency (Hz) PSRR vs. Frequency +0 PSRR vs. Frequency +0 Power Supply Rejection Ratio (dB) Power Supply Rejection Ratio (dB) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 RL=8 AV=12dB Cb=0.22F Ci=0.22F Vrr=0.2Vrms -10 -20 -30 -40 -50 -60 VDD=3.6V RL=8 AV=12dB Ci=0.22F Vrr=0.2Vrms Cb=0.01F Cb=0.1F VDD=2.4V VDD=3.6V VDD=5.0V 1k 10k 20k -70 Cb=0.47F -80 -90 100 Cb=1F 1k 10k 20k 100 -100 20 Frequency (Hz) Frequency (Hz) CMRR vs. Frequency Common Mode Rejection Ratio (dB) +0 CMRR vs. Common Mode Input Voltage +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 1 2 3 4 5 VDD=2.4V VDD=3.6V VDD=5.0V RL=8 AV=12dB fin=1kHz Ci=0.22F Common Mode Rejection Ratio (dB) -10 -20 -30 -40 -50 -60 -70 -80 20 RL=8 AV=12dB Vin=0.2V PP Ci=0.22F VDD=2.4V VDD=3.6V VDD=5.0V 100 1k 10k 20k -100 Frequency (Hz) Common Mode Input Voltage (Vrms) Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 10 www.anpec.com.tw APA2037 Typical Operating Characteristics (Cont.) Frequency Response +14 +260 Frequency Response +14 Gain +220 +260 +12 Gain +12 +220 Phase (deg) Gain (dB) Gain (dB) +10 Phase +8 VDD=5.0V AV=12dB RL=8 Ci=0.22F 10 100 1k 10k 200k +180 +10 Phase +8 VDD=3.6V AV=12dB RL=8 Ci=0.22F 100 1k 10k +180 +140 +140 +6 +100 +6 +100 +4 +60 +4 10 +60 200k Frequency (Hz) Frequency (Hz) Frequency Response +14 Gain +12 +220 8 Supply Current vs. Supply Voltage +260 10 AV=12dB No Load Supply Current (mA) Phase (deg) Gain (dB) +10 Phase +8 VDD=2.4V AV=12dB RL=8 Ci=0.22F 10 100 1k 10k 200k +180 6 +140 4 +6 +100 2 +4 +60 0 2.4 3.0 3.5 4.0 4.5 5.0 5.5 Frequency (Hz) Supply Voltage (V) Start-up Time vs. Bypass Capacitor 200 VDD=5.0V AV=12dB No Load GSM Power Supply Rejection vs. Frequency -40 -80 -120 Start-up Time (ms) 150 100 Output Voltage (dBV) +0 -40 -80 -160 50 -120 -160 0 400 800 1.2k 1.6k 2k 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Bypass Capacitor (F) Frequency (Hz) Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 11 www.anpec.com.tw Supply Voltage (dBV) +0 Phase (deg) APA2037 Operating Waveforms GSM Power Supply Rejection vs. Time VDD 1 VDD Power On 1 VROUT 2 2 VROUT CH1: VDD, 100mV/Div, DC Voltage Offset = 5.0V CH2: VROUT, 20mV/Div, DC TIME: 2ms/Div CH1: VDD, 2V/Div, DC CH2: VROUT, 50mV/Div, DC TIME: 20ms/Div Power Off Shutdown Release VDD VRSD 1 1 2 VROUT 2 VROUTN CH1: VDD, 2V/Div, DC CH2: VROUT, 50mV/Div, DC TIME: 50ms/Div CH1: VRSD, 2V/Div, DC CH2: VROUTN, 2V/Div, DC TIME: 20ms/Div Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 12 www.anpec.com.tw APA2037 Operating Waveforms (Cont.) Shutdown VRSD 1 VROUTN 2 CH1: VRSD, 2V/Div, DC CH2: VROUTN, 2V/Div, DC TIME: 20ms/Div Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 13 www.anpec.com.tw APA2037 Block Diagram LINN LOUTP LOUTN LINP LSD RSD Bias and Control Circuitrys LBYPASS RBYPASS RINP ROUTN ROUTP RINN Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 14 www.anpec.com.tw APA2037 Typical Application Circuits Single-ended input mode VDD Cs2 0.1F 7 LVDD 40k Rf1 Left Channel Input Ci1 0.22F Ci2 0.22F Ri1 10k Ri2 10k 40k Rf2 LSD 9 SHUTDOWN Control RSD 14 RLSD 100k RRSD Ci3 0.22F Right Channel Input Ci4 0.22F Ri3 10kW Ri4 10kW 1 ROUTP RINN 17 40k Rf4 5 GND Gnd 2 GND 4 100k RINP 16 GND Gnd Cs1 10F 19 RVDD LINN 13 4 LOUTP 6 LOUTN LINP 12 4 11 LBYPASS Bias and Control Circuitrys 13 RBYPASS Cb2 40k Rf3 3 ROUTN Cb1 Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 15 www.anpec.com.tw APA2037 Typical Application Circuits (Cont.) Differential input mode VDD Cs2 Cs1 0.1F Gnd 10F 7 LVDD 40k Rf1 Ci1 Left Channel Input 0.22F Ci2 0.22F Ri1 10k Ri2 10k 40k Rf2 LSD 9 SHUTDOWN Control RSD 14 RLSD 100k RRSD Ci3 Right Channel Input 0.22F Ci4 0.22F Ri3 10k Ri4 10k 1 ROUTP RINN 17 40k Rf4 5 GND Gnd 2 GND 4 100k RINP 16 GND 19 RVDD LINN 13 4 LOUTP 6 LOUTN LINP 12 4 11 LBYPASS Bias and Control Circuitrys 13 RBYPASS Cb2 40k Rf3 3 ROUTN Cb1 Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 16 www.anpec.com.tw APA2037 Function Description Fully Differential Amplifier The power amplifiers are fully differential amplifiers with differential inputs and outputs. The fully differential amplifier has some advantages versus traditional amplifiers. First, don' need the input coupling capacitors because t the common-mode feedback compensates the input bias. The inputs can be biased from 0.5V~VDD-0.5V, and the outputs are still biased at mid-supply of the power amplifier. If the inputs are biased at out of the input range, the coupling capacitors are required. Second, the fully differential amplifier has outstanding immunity against supply voltage ripple (217Hz) cuased by the GSM RF transmitters' signal which is better than the typical audio amplifier. Mono Operation The APA2037 has independent shutdown to control each channel' power amplifier, this allows user switching aus dio amplifier to stereo or mono operation and giving flexible control at design. Thermal Protection The over-temperature circuit limits the junction temperature of the APA2037. When the junction temperature exceeds T J = +150 oC, a thermal sensor turns off the amplifiers, allowing the device to cool. The thermal sensor allows the amplifiers to start-up after the junction temperature cools down to about 125 C. The thermal protection is designed with a 25 oC hysteresis to lower the average TJ during continuous thermal overload conditions, increasing lifetime of the IC. Over-Current Protection The APA2037 monitors the output buffers'current. When the over current occurs, the output buffers'current will be reduced and limited to a fold-back current level. The power amplifier will go back to normal operation until the over-current situation has been removed. In addition, if the over-current period is long enough and the IC' s junction temperature reaches the thermal protection threshold, the IC enters thermal protection mode. Shutdown Function The APA2037 has separated shutdown control for each channel. User can shutdown left channel amplifier by LSD, or shutdown right channel amplifier by RSD. If all the amplifiers are shutdown, APA2037 only consumes 1A typical.. Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 17 o Application Information Input Resistance (Ri) The gain for the APA2037 is set by the external input resistors (Ri) and internal feedback resistors (Rf). AV = Rf Ri (1) The internal feedback resistors are 40k typical. For the performance of a fully differential amplifier, it' better to s select matching input resistors R i1 , Ri2 , Ri3 ,and R i4 . Therefore, 1% tolerance resistors are recommended. If the input resistors are not matched, the CMRR and PSRR performance are worse than using matching devices. Input Capacitor (Ci) When the APA2037 is driven by a differential input source, the input capacitor may not be required. In the single-ended input application, an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the input resistance Ri form a high-pass filter with the corner frequency determined in the following equation: 1 FC(highpass) = (2) 2R iCi The value of Ci must be considered carefully because it directly affects the low frequency performance of the circuit. Consider the example where Ri is 10k and the specification that calls for a flat bass response down to 100Hz. The equation is reconfigured below: Ci = 1 2RiFc (3) Consider the input resistance variation, the Ci should be 0.16F. Therefore, one would likely choose a value in the range of 0.22F to 0.47F. A further consideration for this capacitor is the leakage path from the input source through the input network (Ri + Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input of the amplifier. The offset reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications because the DC level of the amplifiers' inputs are held at VDD/2. Please note that it is important to confirm the capacitor polarity in the application. www.anpec.com.tw APA2037 Application Information (Cont.) Effective Bypass Capacitor (CBYPASS) The BYPASS pin sets the VDD/2 for internal reference by voltage divider. Adding capacitors at this pin to filter the noise and regulator the mid-supply rail will increase the PSRR and noise performance. The capacitors should be as close to the device as possible. The effect of a larger bypass capacitor will improve PSRR due to increased supply stability. The bypass capacitance also affects to the start time. The large capacitors will increase the start time when device exist shutdown. Optimizing Depop Circuitry Circuitry has been included in the APA2037 to minimize the amount of popping noise at power-up and when coming out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to eliminate clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the device or the shutdown function will cause the click and pop circuitry. The value of Ci will also affect turn-on pops. The bypass voltage ramp up should be slower than input bias voltage. Although the BYPASS pin current source cannot be modified, the size of CBYPASS can be changed to alter the device turn-on time and the amount of clicks and pops. By increasing the value of CBYPASS, turn-on pop can be reduced. However, the tradeoff for using a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relationship between the size of CBYPASS and the turn-on time. A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain. Hence, it is advantageous to use low-gain configurations. Power Supply Decoupling Capacitor (Cs) The APA2037 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD+N) is as low as possible. Power supply decoupling also prevents the oscillations caused by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by using two different types of capacitors that target on different types of noises on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series- resistance (ESR) ceramic capacitor, typically 0.1F, is placed as close as possible to the device VDD lead works best. For filtering lower frequency noise signals, a large aluminum electrolytic capacitor of 10F or greater placed near the audio power amplifier is recommended. Fully Differential Amplifier Efficiency The traditional class AB power amplifier efficiency can be calculated starts out as being equal to the ratio of power from the power supply to the power delivered to the load. The following equations are the basis for calculating amplifier efficiency. P (4) Efficiency () = O PSUP where: PO = VOrms V =P RL 2RL VP 2 (5) 2 2 VOrms = 2V V PSUP = VDD XIDD] DD PP AVG RL IDD] AVG) = 2VP RL VP 2PORL 4VDD 4VDD So the Efficiency () is: Efficiency ( ) = (6) Table 1 calculates efficiencies for four different output power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a stereo 1W audio system with 8 loads and a 5V supply, the maximum draw on the power supply is almost 1.63W. Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 18 www.anpec.com.tw APA2037 Application Information (Cont.) Fully Differential Amplifier Efficiency (Cont.) R L () P O (W) 0.25 0.50 1 1.6 0.4 1.2 2 2.6 0.5 1 2 3 Efficiency (%) 30.1 43.1 61.5 77.7 27.5 48.1 62.4 74.1 27.5 38.7 55.1 66.8 IDD(A) 0.17 0.23 0.33 0.43 0.29 0.51 0.66 0.70 0.37 0.52 0.74 0.92 P D (W) P SUP (W) 0.58 0.66 0.63 0.46 1.06 1.30 1.21 0.91 1.32 1.58 1.63 1.49 0.83 1.16 1.63 2.06 1.46 2.50 3.21 3.51 1.82 2.58 3.63 4.49 1. All components should be placed close to the APA2037. For example, the input capacitor (Ci) should be close to APA2037' input pins to avoid causing noise cous pling to APA2037' high impedance inputs; the s decoupling capacitor (Cs ) should be placed by the APA2037' power pin to decouple the power rail noise. s 2. The output traces should be short, wide ( >50mil), and symmetric. 3. The input trace should be short and symmetric. 4. The power trace width should greater than 50mil. 5. The TQFN5X5-20A Thermal PAD should be soldered on PCB, and the ground plane needs soldered mask (to avoid short circuit) except the Thermal PAD area. 8 4 3 Table 1: Efficiency vs. Output Power in 5-V Differential Amplifier Syetems A final point to remember about linear amplifiers (either SE or Differential) is how to manipulate the terms in the efficiency equation to utmost advantage when possible. Note that in equation, VDD is in the denominator. This indicates that as VDD goes down, efficiency goes up. In other words, use the efficiency analysis to choose the correct supply voltage and speaker impedance for the application. Layout Recommendation 1mm 0.49mm ThermalVi a diameter 0.3mm X 9 0.65mm 3.1mm Solder Mask to Prevent Short Circuit Ground plane for Thermal PAD Figure 5. TQFN5x5-20A Land Pattern Recommendation Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 5.8mm 4.8mm 19 www.anpec.com.tw APA2037 Package Information TQFN5x5-20A D A Pin 1 E D2 A1 A3 e S Y M B O L A A1 A3 b D D2 E E2 e L K 0.45 0.20 0.25 4.90 3.00 4.90 3.00 0.65 BSC 0.65 0.018 0.008 TQFN5x5-20A MILLIMETERS MIN. 0.70 0.00 0.20 REF 0.35 5.10 3.40 5.10 3.40 0.010 0.193 0.118 0.193 0.118 0.026 BSC 0.026 MAX. 0.80 0.05 MIN. 0.028 0.000 0.008 REF 0.014 0.201 0.134 0.201 0.134 INCHES MAX. 0.031 0.002 Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 20 Lk E2 Pin 1 Corner b www.anpec.com.tw APA2037 Carrier Tape & Reel Dimensions OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B d Application A 330.0O .00 2 H 50 MIN. P1 8.0O .10 0 H A T1 T1 C d 1.5 MIN. D1 1.5 MIN. D 20.2 MIN. T 0.6+0.00 -0.40 W W E1 F 5.5O .10 0 K0 1.30O .20 0 12.4+2.00 13.0+0.50 -0.00 -0.20 P2 2.0O .05 0 D0 1.5+0.10 -0.00 12.0O .30 1.75O .10 0 0 A0 5.30O .20 0 B0 5.30O .20 0 TQFN5x5-20A P0 4.0O .10 0 (mm) Devices Per Unit Package Type TQFN5x5-20A Unit Tape & Reel Quantity 2500 Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 21 www.anpec.com.tw APA2037 Taping Direction Information TQFN5x5-20A USER DIRECTION OF FEED Reflow Condition TP (IR/Convection or VPR Reflow) tp Critical Zone TL to TP Ramp-up TL Temperature tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25C to Peak Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 22 Time Description 245C, 5 sec 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA www.anpec.com.tw Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 APA2037 Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Time 25C to Peak Temperature Sn-Pb Eutectic Assembly 3C/second max. 100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds 6C/second max. 6 minutes max. Pb-Free Assembly 3C/second max. 150C 200C 60-180 seconds 217C 60-150 seconds See table 2 20-40 seconds 6C/second max. 8 minutes max. Note: All temperatures refer to topside of the package. Measured on the body surface. Table 1. SnPb Eutectic Process - Package Peak Reflow Temperatures Volume mm <350 <2.5 mm 240 +0/-5C 2.5 mm 225 +0/-5C Table 2. Pb-free Process - Package Classification Reflow Temperatures Package Thickness 3 3 3 Volume mm 350 225 +0/-5C 225 +0/-5C 3 Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0C* 260 +0C* 260 +0C* 1.6 mm - 2.5 mm 260 +0C* 250 +0C* 245 +0C* 2.5 mm 250 +0C* 245 +0C* 245 +0C* * Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level. Package Thickness 3 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright (c) ANPEC Electronics Corp. Rev. A.2 - Aug., 2008 23 www.anpec.com.tw |
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